1. Field of the Invention
This invention relates to digital data transmission systems, and more particularly, to a digital data transmission system of the type that might include a digital data slicer whose output sliced signal is based on feedback control using a digital sum value (DSV) of the output sliced signal.
2. Description of the Related Art
In digital data transmission systems, such as those used in transferring data within computers and over data networks, the appearance of a DC (direct current) component in the transmitted binary signal is highly undesirable. The DC component is the result of an unequal number of 1's and 0's in the transmitted binary signal. To minimize the DC component in the transmitted binary signal, a number of coding methods have been proposed which substitute symbols in the data stream with other symbols so that the number of 1's and 0's in the modified data stream is more nearly equal on a running basis. For instance, U.S. Pat. No. 4,833,471 discloses a coding method which can make the digital sum value (DSV) of the encoded binary data to approach zero before being transmitted. Additionally, the Red Book IEC-908 for CD-ROM data transmission specifies several standards that can make the DSV of encoded binary data approach zero.
Various conventional digital data slicers are available. Three conventional digital data slicers are illustrated and described in detail respectively in the following with reference to FIG. 1, FIG. 2, and FIG. 3. FIG. 1 is a schematic block diagram of a first conventional digital data slicer which includes a comparator 10 and a low-pass filter (LPF) 12. The comparator 10 has two input terminals: a first terminal receiving an input signal X.sub.I1 and a second input terminal receiving a reference slice level V.sub.C1. The reference slice level V.sub.C1, is obtained by passing the output X.sub.O1, of the comparator 10 through the LPF 12. The output X.sub.O1, of the comparator 10 is referred to as a sliced signal and is the output of the digital data slicer. When the input signal X.sub.I1 is greater than the reference slice level V.sub.C1, the comparator 10 outputs a high voltage level representing a first binary logic value; when X.sub.I1 is lower than V.sub.C1, the comparator 10 outputs a low voltage level representing a second binary logic value.
FIG. 2 is a schematic block diagram of a second conventional digital slicer which also includes a comparator 20 having two input terminals: a first terminal receiving an input signal X.sub.I2 and a second input terminal receiving a reference slice level V.sub.C2. This digital data slicer differs from the previous one shown in FIG. 1 in that the reference slice level V.sub.C2 is obtained by processing the output of the comparator 20, here designated by X.sub.O2, through a phase-locked loop (PLL) 22 and a digital-to-analog (D/A) converter 24. The output X.sub.O2 of the digital data slicer is once again the sliced signal. Under control of the clock signal K.sub.2, the phase-locked circuit 22 converts the sliced signal X.sub.O2 into a phase error 23. This phase error 23 is then converted by the D/A converter 24 into the reference slice level V.sub.C2 which is provided to the comparator 20. When the input signal X.sub.I2 is greater than the reference slice level V.sub.C2, the comparator 20 outputs a high voltage level representing a first binary logic value; when X.sub.I2 is lower than V.sub.C2, the comparator 20 outputs a low voltage level representing a second binary logic value. In an alternate embodiment of the digital slicer of FIG. 2, the D/A converter 24 can be replaced by an integrator or a current source.
For the two conventional digital data slicers shown in FIGS. 1 and 2, if the data rate of the input signal is changed, the working bandwidth of the digital data slicers should be adjusted accordingly to provide optimal performance. If the digital data slicer is based on analog circuitry, the bandwidth adjustment is difficult to carry out and the selection of an appropriate bandwidth is limited because only a limited range of bandwidths are available for the adjustment. If the digital data slicer is based on digital circuitry, the hardware required to allow for adjustment of the bandwidth is costly to implement. In most practical applications, the accuracy of the output of the digital data slicer will be degraded when the bandwidth of the input signal varies from its nominal design range.
FIG. 3 is a schematic block diagram of a third conventional digital data slicer which is based on a comparator 30 having two input terminals: a first terminal receiving an input signal X.sub.I3 and a second input terminal receiving a reference slice level V.sub.C3. This digital data slicer differs from the previous two shown in FIGS. 1 and 2 in that the output of the comparator 30, here designated by X.sub.O3, is processed by an up/down counter 32, a digital-to-analog (D/A) converter 34, and a frequency divider 36 to obtain the reference slice level V.sub.C3. The sliced signal X.sub.O3 is fed to the up/down counter 32 which is controlled by a clock signal K.sub.3 output by the frequency divider 36. The clock signal K.sub.3 is the output of the frequency divider 36 which divides an input clock signal NK.sub.3 by a factor of N. The up/down counter 32 operates in such a manner that when the sliced signal X.sub.O3 is at a first binary value (for example, 0) upon clock signal K.sub.3 switching, the stored content of the up/down counter 32 is decreased by one. When the sliced signal X.sub.O3 is at a second binary value (for example, 1) upon clock signal K.sub.3 switching, the stored content of the up/down counter 32 is increased by one. The content of the up/down counter 32, which is a digital value, is output to the D/A converter 34 where the digital value is converted into an analog signal. The analog signal from the D/A converter 34 then serves as the reference slice level V.sub.C3 provided as an input to the comparator 30. When the input signal X.sub.I3 is greater than the reference slice level V.sub.C3, the comparator 30 outputs a high voltage level represent a first binary logic value; when X.sub.I3 is lower than V.sub.C3, the comparator 20 outputs a low voltage level representing a second binary logic value.
In the digital data slicer of FIG. 3, the frequency divider 36 must be used to reduce the source frequency NK.sub.3 to the frequency output K.sub.3 because the D/A converter 34 has a limited bandwidth. One drawback to the use of the frequency divider is that it causes a delay and thus reduces the processing speed. Use of the frequency divider also reduces the accuracy of the digital data slicer.